Converters.TV 722 Specifications download pdf

RGB to NTSC/PAL Encoder

AD722

One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.

Tel: 617/329-4700 Fax: 617/326-8703

FEATURES

Low Cost, Integrated Solution

+5 V Operation

Accepts FSC Clock or Crystal, or 4FSC Clock

Composite Video and Separate Y/C (S-Video) Outputs

Minimal External Components:

No External Filters or Delay Lines Required

Onboard DC Restoration

Accepts Either HSYNC & VSYNC or CSYNC

Phase Lock to External Subcarrier

Drives 75 Ω Reverse-Terminated Loads

Logic Selectable NTSC or PAL Encoding Modes

Compact 16-Pin SOIC

APPLICATIONS

RGB to NTSC or PAL Encoding

PRODUCT DESCRIPTION

The AD722 is a low cost RGB to NTSC/PAL Encoder that

converts red, green and blue color component signals into their

corresponding luminance (baseband amplitude) and chromi-

nance (subcarrier amplitude and phase) signals in accordance

with either NTSC or PAL standards. These two outputs are

also combined to provide composite video output. All three out-

puts can simultaneously drive 75 Ω, reverse-terminated cables.

All logical inputs are CMOS compatible. The chip operates

from a single +5 V supply. No external delay lines or filters are

required. The AD722 may be powered down when not in use.

The AD722 accepts either FSC or 4FSC clock. When a clock is

not available, a low cost parallel-resonant crystal (3.58 MHz

(NTSC) or 4.43 MHz (PAL)) and the AD722’s on-chip oscilla-

tor generate the necessary subcarrier clock. The AD722 also ac-

cepts the subcarrier clock from an external video source.

The interface to VGA Controllers and MPEG Video Decoders

is simple: an on-chip logic “XNOR” accepts the available verti-

cal (VSYNC) and horizontal sync (HSYNC) signals and creates

the composite sync (CSYNC) signal on-chip. If available, the

AD722 will also accept a standard CSYNC signal by connecting

VSYNC to +5 V and applying CSYNC to HSYNC pin. The

AD722 contains decoding logic to identify valid HSYNC pulses

for correct burst insertion.

Delays in the U and V chroma filters are matched by an on-chip

sampled-data delay line in the Y signal path. To prevent

aliasing, a prefilter at 5 MHz is included ahead of the delay line

and a post-filter at 5 MHz is added after the delay line to sup-

press harmonics in the output. These low-pass filters are opti-

mized for minimum pulse overshoot. The overall luma delay,

relative to chroma, has been designed to be 170 ns, which

precompensates for delays in the filters used in the IF section of

a television receiver. This precompensation delay is already

present in TV broadcasts. The AD722 comes in a space-saving

SOIC and is specified for the 0°C to +70°C commercial tem-

perature range.

FUNCTIONAL BLOCK DIAGRAM

PHASE

DETECTOR

CHARGE

PUMP

FILTER

LOOP

XOSC

4FSC

VCO

SYNC

SEPARATOR

XNOR

XOSC

CHARGE

PUMP

FILTER

LOOP

4FSC

VCO

XNOR

4FSC

FSC

SUB-

CARRIER

NTSC/PAL

HSYNC

VSYNC

BURST

QUADRATURE

DECODER

±180°

(PAL ONLY)

NTSC/PAL

FSC 90

FSC 0

4FSC

SC 90

/270

FSC

CSYNC

CLAMP

RED

GREEN

BLUE

RGB-TO-YUV

ENCODING

MATRIX

BURST

Y 3-POLE

LP PRE-

FILTER

4-POLE

LPF

4-POLE

LPF

BALANCED

MODULATORS

3-POLE LPF

3.6MHz (NTSC)

4.4MHz (PAL)

NTSC/PAL

CSYNC

INSERTION

SAMPLED-

DATA

DELAY

LINE

2-POLE

LP POST-

FILTER

LUMINANCE

OUTPUT

COMPOSITE

OUTPUT

CHROMINANCE

OUTPUT

CLAMP

NTSC/PAL

CLOCK

AT 4FSC

CLAMP

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

1 2 3 4 5 6 ... 11 12

Summary of Contents

Page 1 - RGB to NTSC/PAL Encoder

aRGB to NTSC/PAL EncoderAD722© Analog Devices, Inc., 1995One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.Tel: 617/329-4700 Fax: 617/

Page 2 - AD722–SPECIFICATIONS

REV. 0–10–AD722Figure 15 shows a circuit for connection to the VGA port of aPC. The RGB outputs connect directly to the respective inputsof the AD722.

Page 3 - WARNING!

AD722REV. 0–11–The IF strips used in TVs delay the chrominance by 170 nsmore than the luminance. To compensate for this, transmittedvideo has the chro

Page 4 - Circuit D

REV. 0–12–AD722Synchronous vs. Asynchronous OperationThe source of RGB video and synchronization used as an inputto the AD722 in some systems is deriv

Page 5 - Typical Characteristics–AD722

AD722–SPECIFICATIONSREV. 0–2–(Unless otherwise noted, VS = +5, TA = +25°C, using FSC synchronous clock. All loads are150 Ω ± 5% at the IC pins. Output

Page 6 - AD722–Typical Characteristics

AD722REV. 0–3–ORDERING GUIDETemperature Package PackageModel Range Description OptionAD722JR-16 0°C to +70°C 16-Pin SOIC R-16AD722JR-16-Reel 0°C to +7

Page 7 - THEORY OF OPERATION

REV. 0–4–AD722PIN DESCRIPTIONSPin Mnemonic Description Equivalent Circuit1 STND A Logical HIGH input selects NTSC encoding. Circuit AA Logical LOW inp

Page 8 - APPLYING THE AD722

REV. 0–5–IREµs0.100.5–0.506010 20 30 40 500.0APL = 50.8%525 LINE NTSC NO FILTERINGSLOW CLAMP TO 0.00V @ 6.63µsPRECISION MODE OFF SY

Page 9 - Layout Considerations

REV. 0–6–AD722–Typical Characteristics1ST 2ND 3RD 4TH 5TH 6TH0.00 –0.16 –0.49 –0.53 –0.52 –0.380.00 –0.44 –1.14 –1.01 –0.53 –0.01DG DP (NTSC) (SYNC =

Page 10 - AD722 APPLICATION DISCUSSION

AD722REV. 0–7–9.72µs5.49µs4.59µs39.7 IRE33.8 IRE9.0 CYCLESH TIMING MEASUREMENT RS–170A (NTSC)FIELD = 1 LINE = 22AVERAGE 256 ≥ 256124ns100nsFigure

Page 11 - Dot Crawl

REV. 0–8–AD722The other analog path is the chrominance path which is wherethe U and V color difference signals are processed. The U and Vsignals first

Page 12 - Figure 17

AD722REV. 0–9–resistor is required close to each AD722 output, while 75 Ω toground should terminate the far end of each line.The outputs have a dc bia

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